Imaging sensors comprise an array of unit elements (pixels). The array of pixels is exposed to radiation during an exposure period and, subsequently, the signal value of each pixel is read from the array. The array can be a one dimensional array (linear sensor) or a two dimensional array (area array) with pixels arranged in rows and columns.
FIG. 1 shows the typical architecture of a CMOS imaging sensor. Impinging photons are converted into charges in the pixel array 10 and are accumulated during a certain integration period. Typically, the pixels are selected row by row for readout of their signals. A typical four transistor (4T) pixel is shown in FIG. 2. The pixel includes a photodiode PD, a transfer gate to transfer the charges in the photodiode to the floating diffusion FD, a reset transistor M1, a source follower M2 and a row selection transistor M3. The reset transistor M1 is used to reset the floating diffusion FD to a known state before transferring charge from the photodiode PD to it as is known in the art. The source follower M2 converts the charges stored at the floating diffusion FD into an electrical output voltage signal at the column bus. The useful signal outputs of a pixel are analog voltages representing: (i) the reset signal level Vreset and (ii) the signal level Vsig that is generated after charge transfer from the photodiode. The final signal that represents the amount of photons impinged onto the pixel is the difference signal between these two signals. In the sensor of FIG. 1, there is sample and hold circuitry 15 associated with each column of the array. During the process of reading the array, the sample and hold circuitry 15 for each column stores the two signal values (Vreset, Vsig) for a pixel in a selected row. The two signals (Vreset, Vsig), or the difference between these signals (Vreset−Vsig), must be converted from an analog value to a digital value. In FIG. 1 the analog-to-digital conversion is performed by a single ADC 16 in the output stage of the array and this single ADC 16 is used, on a time-shared basis, by the column circuits. In turn, signal values are transferred from each of the column circuits to the ADC 16 and converted to digital form.
FIG. 3 shows an alternative approach. Analog-to-digital conversion is performed, in parallel, in each column of the array. The single-slope ADC comprises a ramp generator 20 and a synchronous counter 17. Each column has two data latches 18 and a comparator 19. A ramp signal is applied to each of the columns circuits. The ramp signal is distributed to all columns. The counter 17 is incremented in synchronism with the ramp signal such that, at any point in time, the counter 17 provides a digital representation of the analog value of the ramp signal output by the ramp generator 20. The comparator 19 in each column compares the level of the input signal (Vreset or Vsig) against the gradually changing ramp signal. When the ramp voltage reaches the value of the input signal voltage, the comparator 19 output changes state and latches the digital code of the counter into a first memory 18. Afterwards, the same process is repeated for the other of the signals (Vreset, Vsig) and the code is latched into a second memory 18. The difference in digital codes is then sent to the output of the sensor.
A refinement of this arrangement is described in U.S. Pat. No. 7,088,279 and U.S. Pat. No. 7,321,329 and shown in FIG. 4. The circuitry associated with each column is provided with a dedicated counter 31 which is able to count in a downwards direction and in an upwards direction. When converting the reset signal Vreset, the counter 31 counts down until the ramp signal reaches the reset level. The direction of counting of the counter 31 is then switched. During the next ramp signal, the counter 31 counts up until the level of the light induced signal Vsig is reached. The technique is depicted in FIG. 5. This architecture has some advantages compared to the conventional architecture. In the conventional architecture, the code generated by counter 17 needs to be distributed over the columns. Column-to-column variations of clock skew, which cause conversion error, are generated when a high-speed clock is used. Both reset level and signal level include offset noise from pixel, column circuitry and comparator, the ADC automatically performs the calculation of the difference between the reset and signal values and no additional subtraction circuitry is required. Ripple counters can be used in this architecture because it is unnecessary for them to be synchronized with the high-speed clock. Column-to-column variations of clock skew and counter delay which cause A/D conversion error are corrected for.
It is desirable that the analog-to-digital conversion occurs as quickly as possible. The rate at which the ADC can operate is limited by several constraints. A significant constraint is the period of the ramp signal against which the analog reset level and signal level are compared. The gradient of the ramp signal Vramp signal can be increased but, for a given resolution (number of bits), it is necessary to proportionally increase the frequency of the master clock that is distributed to the counters in the column processing units. In practice, there is a limit to the clock frequency that can be achieved.
The present invention seeks to provide an alternative way of performing analog-to-digital conversion.